`timescale  1ns/1ns
module sim_audio  ;

wire audio_ws;
wire audio_bck;
wire audio_din;

reg sys_clk;
reg sys_rst;
wire fifo_read_en;
reg [3:0] counter;
always #5 sys_clk <= ~sys_clk;

initial begin
    #0 begin sys_clk <= 0; sys_rst <= 1'b1; end
    #50 sys_rst <= 1'b0;
end

reg [31:0 ] audio_data [3:0];

initial begin
    audio_data[0] = 32'h11112222;
    audio_data[1] = 32'h5555aaaa;
    audio_data[2] = 32'h00000000;
    audio_data[3] = 32'hbbbbeeee;
end

always @ (posedge sys_clk)
    if(sys_rst)
        counter <= 0;
    else if(fifo_read_en) begin
        counter <= counter + 1;
        if(counter == 3)
            $finish();
    end

LSBJ_audio_driver # (
    .DEF_LEN(24),
    .WIDTH(16),
    .FIFO_DELAY_MIN(3)
) dut (
    .audio_clk  (sys_clk), // Double rate of DEF_LEN * audio_bck
    .reset      (sys_rst),

    .left_data  (audio_data[counter][15:0]),
    .right_data (audio_data[counter][31:16]),
    .fifo_read_en(fifo_read_en),
    .fifo_read_ready(1'b1),

    .audio_ws   (audio_ws),
    .audio_bck  (audio_bck),
    .audio_din  (audio_din)

);

initial
begin            
    $dumpfile("wave.vcd");        //生成的vcd文件名称
    $dumpvars(0, sim_audio);    //tb模块名称
end

endmodule
